1
Hui Angela T: In-situ surface treatment for memory cell formation. Advanced Micro Devices, Hui Angela T, DRAKE Paul S, November 3, 2005: WO/2005/104187 (1 worldwide citation)

A system and methodology are disclosed for forming a passive layer on a conductive layer, such as can be done during fabrication of an organic memory cell, which generally mitigates drawbacks inherent in conventional inorganic memory devices. The passive layer includes a conductivity facilitating co ...


2
Oglesby Jane V, Lyons Christopher F, Subramanian Ramkumar, Hui Angela T, Ngo Minh Van, Pangrle Suzette: Spin on polymers for organic memory devices. Advanced Micro Devices, Oglesby Jane V, Lyons Christopher F, Subramanian Ramkumar, Hui Angela T, Ngo Minh Van, Pangrle Suzette, sCOLLOPY Daniel R, February 17, 2005: WO/2005/015635

A method of making organic memory cells (104) made of two electrodes (106, 108) with a controllably conductive media (110) between the two electrodes (106, 108) is disclosed. The controllably conductive media (110) contains an organic semiconductor layer (112) and passive layer (114). The organic se ...


3
Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010892

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


4
Fang Shenqing, Thurgate Timothy, Chang Kuo Tung, Fastow Richard, Hui Angela T, Mizutani Kazuhiro, Ko Kelwin, Kinoshita Hiroyuki, Sun Yu, Ogawa Hiroyuki: Structure and method for low vss resisitance and reduced dibl in a floating gate memory cell. Spansion, Fang Shenqing, Thurgate Timothy, Chang Kuo Tung, Fastow Richard, Hui Angela T, Mizutani Kazuhiro, Ko Kelwin, Kinoshita Hiroyuki, Sun Yu, Ogawa Hiroyuki, sDRAKE Paul S, August 11, 2005: WO/2005/074018

According to one exemplary embodiment, a floating gate memory cell (202) comprises a stacked gate structure (208) situated on a substrate (204) and situated over a channel region (222) in the substrate (204). The floating gate memory cell (202) further comprises a recess (228) formed in the substrat ...


5
Chan Darin A, Chan Simon S, Hui Angela T: Method of forming planarized shallow trench isolation. Advanced Micro Devices, Chan Darin A, Chan Simon S, Hui Angela T, DRAKE Paul S, August 11, 2005: WO/2005/074023

Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill (25) with respect to the polish stop film (23) prior to removing the polish stop film (23). Embodiments include etching back a silicon oxide trench fill (25) to a depth of about 200 Å to about 1 ...


6
Ngo Minh Van, Joshi Amol Ramesh, Li Wenmei, Cheng Ning, Takagi Norimitsu, Hui Angela T, Agarwal Ankur Bhushan: Contact spacer formation using atomic layer deposition. Spansion, Advanced Micro Devices, Ngo Minh Van, Joshi Amol Ramesh, Li Wenmei, Cheng Ning, Takagi Norimitsu, Hui Angela T, Agarwal Ankur Bhushan, JAIPERSHAD Rajendra, April 12, 2007: WO/2007/041108

A contact structure in a semiconductor device includes a layer of dielectric material (410) and a via (510) formed through the dielectric material (410). The contact structure further includes a spacer (710) formed on sidewalls of the via (510) using atomic layer deposition (ALD) and a metal (905) d ...


7
Yang Jean, Sun Yu, Ramsbey Mark T, Weidong Qian, Hui Angela T: Bit line implant. Spansion, Advanced Micro Devices, Yang Jean, Sun Yu, Ramsbey Mark T, Weidong Qian, Hui Angela T, JAIPERSHAD Rajendra, April 26, 2007: WO/2007/047265

A method for performing a bit line implant is disclosed. The method includes forming a group of structures (1410) on an oxide-nitride-oxide stack (1220, 1230, 1240) of a semiconductor device (1200). Each structure of the group of structures includes a polysilicon portion (1250) and a hard mask porti ...


8
Kim Unsoon, Hui Angela T, Wu Yider, Chang Kuo Tung, Kinoshita Hiroyuki: System and method for improving mesa width in a semiconductor device. Spansion, Advanced Micro Devices, Kim Unsoon, Hui Angela T, Wu Yider, Chang Kuo Tung, Kinoshita Hiroyuki, JAIPERSHAD Rajendra, February 8, 2007: WO/2007/015987

A method for forming a memory device ( 100) is provided. A nitride layer (330) is formed over a substrate (310). The nitride layer (330) and the substrate (310) are etched to form a trench (510). The nitride layer (330) is trimmed on opposite sides of the trench (510) to widen the trench (510) withi ...



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