1
Calogero Mantellina, Daniele Zanzottera, Marco Gelmetti: Memory module selection and reconfiguration apparatus in a data processing system. Honeywell Information Systems Italia, Nicholas Prasinos, John S Solakian, February 18, 1986: US04571676 (59 worldwide citation)

A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initial ...


2
Giorgio Costantini: Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates. Honeywell Information Systems Italia, John S Solakian, Nicholas Prasinos, September 15, 1987: US04694394 (55 worldwide citation)

A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection ...


3
Bardotti Angelo, Pederzini Renzo: Dynamically variable priority access system. Honeywell Information Systems Italia, Elbinger Esq Lewis P, Reiling Esq Ronald T, December 9, 1975: US3925766 (50 worldwide citation)

Apparatus for variably assigning relative priority levels for access of peripheral units to the memory of a data processing system, wherein each peripheral unit generates a request signal when it requires access to communicate with the memory through a channel connected to the central processor of t ...


4
Claudio Gentili, Calogero Mantellina, Alessandro Scotti: Memory with selective intervention error checking and correcting device. Honeywell Information Systems Italia, Finnegan Henderson Farabow Garrett & Dunner, February 3, 1981: US04249253 (44 worldwide citation)

A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path includ ...


5
Guarnaschelli Gianpiero: Memory pre-driver circuit. Honeywell Information Systems Italia, August 14, 1973: US3753008 (41 worldwide citation)

Alow power dissipating monolithic integrated core memory driver circuit for driving memory line transistor switches. The circuit is supplied with two distinct voltage levels and a control circuit responsive to input signals for processing the proper voltage required to effect the selection of a memo ...


6
Filippazzi Franco, Forlani Franco: Connection means for semiconductor components and integrated circuits. Honeywell Information Systems Italia, George V Eltgroth et al, January 22, 1974: US3787252 (39 worldwide citation)

In a semiconductor wafer having an epitaxial layer on which circuit elements are formed, through-connections for said circuit elements to contacts formed on the opposite surface of the layer are provided by tapered high conductivity semiconductor regions insulated from the body by a thin layer of di ...


7
Ezio Cislaghi, Alessandro Scotti, Renzo Pederzini: Semiconductor dynamic memory and related refreshing system. Honeywell Information Systems Italia, August 8, 1978: US04106108 (39 worldwide citation)

A semiconductor memory is provided with means for refreshing the memory. Interrupt requests generated by the memory initiate refreshing cycles, which take place in parallel with normal read/write memory operations. The memory is divided in two parts or blocks. If the central processor unit assigns a ...


8
Pier G Cavallari: Electromagnet assembly for mosaic printing head and related manufacturing method. Honeywell Information Systems Italia, Nicholas Prasinos, February 28, 1984: US04433927 (37 worldwide citation)

An electromagnet assembly for a matrix printing head which can be automatically assembled and a manufacturing process for automatically assembly said electromagnet assembly.


9
Franco Ciacci, Vincenzo Pizzoferrato, Giancarlo Tessera: Data processing system architecture. Honeywell Information Systems Italia, George Grayson, John S Solakian, William A Linnell, May 12, 1987: US04665483 (36 worldwide citation)

Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectio ...


10
Calogero Mantellina, Roberto Trivella, Andrea Quadraruopolo: Memory mapping method in a data processing system. Honeywell Information Systems Italia, Nicholas Prasinos, John S Solakian, May 27, 1986: US04592011 (34 worldwide citation)

In a data processing system wherein a memory is comprised of an unknown plurality of memory blocks of a basic capacity, arranged in an unknown plurality of modules which have an unknown capacity multiple of the basic capacity, a method addresses the memory location which involves the selection of th ...