1
Masataka Takano, Yoji Oka, Akihiko Takase, Setsuo Takahashi: Path changing system and method for use in ATM communication apparatus. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, February 4, 1997: US05600630 (132 worldwide citation)

An ATM path changing system and method for use in an ATM communication apparatus and ATM communication network are provided which can set an alternating route in the event of a failure occurring in a transmission line or VP. A header converter in a line controller includes a plurality of output path ...


2
Yumiko Nishi, Yutaka Torii, Norihumi Komatu, Seiichi Takaki: Bit synchronization circuit. Hitachi, Hitachi Communication Systems, Antonelli Terry Stout & Kraus, June 4, 1991: US05022057 (47 worldwide citation)

A telephone exchange system has a plurality of bit synchronization circuit each provided for an individual subscriber's line. A single clock generating circuit which generates a plurality of clocks is provided in common to the plurality of bit synchronization circuits. The bit synchronization circui ...


3
Masao Mizukami, Nobuaki Kanazawa: A ternary signal transmission circuit and method. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, August 22, 1995: US05444740 (34 worldwide citation)

A signal transmission system provides stable, fast, long-range transmission. During transmission, a short-width pulse is synchronized with rising and falling edges of a transmission pulse signal. A ternary output signal in a differential shape is produced on the basis of the pulse, and an output sig ...


4
Tohru Kazawa, Toshiro Suzuki, Takashi Morita, Souichi Yamashima: Timing extraction circuit and communication system utilizing the same. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, August 17, 1993: US05237590 (32 worldwide citation)

A timing clock extraction circuit for extracting from a multilevel code signal, transmitted at a predetermined baud rate, in which cross timings with a reference level are generated at frequency timings several times the baud rate, a clock pulse train at the baud rate and obtaining discriminative da ...


5
Nobuaki Kanazawa, Masao Mizukami, Kunihiro Ito: Signal receiving circuit and digital signal processing system. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, March 9, 1999: US05880601 (29 worldwide citation)

A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied ...


6
Kouichi Matsushita, Tomio Furuya, Tetsuaki Adachi, Hitoshi Akamine, Nobuhiro Matsudaira: High-frequency power amplifier, wireless communication apparatus and wireless communication system. Hitachi, Hitachi Communication Systems, Miles & Stockbridge P C, August 12, 2003: US06605999 (22 worldwide citation)

A wireless communication apparatus, which is designed to control the output power without using the power control signal sent from the base station, comprises a high-frequency power amplifier for transmission, a detection means which measures the output power of the power amplifier, and an automatic ...


7
Masashi Hiraiwa, Satoru Inazawa, Tatsuo Mochinaga, Kenji Kawakita: Cell/ packet assembly and disassembly apparatus and network system. Hitachi, Hitachi Communication Systems, Antonelli Terry Stout & Kraus, March 31, 1998: US05734653 (20 worldwide citation)

A cell/packet assembly and disassembly apparatus is provided for efficiently connecting a line in a line switching system to an ATM network or a packet network, without causing congestion, to transmit and receive cells or packets therebetween. The cell/packet assembly and disassembly apparatus, upon ...


8
Yoshikuni Matsunaga, Toshihiko Shimizu, Tomio Furuya, Nobuhiro Matsudaira, Koichi Matsushita: High frequency power amplifier circuit device. Renesas Technology, Hitachi Communication Systems, Mattingly Stanger & Malur P C, July 6, 2004: US06759906 (20 worldwide citation)

A multistage high frequency power amplifier circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in ...


9
Kouichi Yamazaki, Setsuo Ogura, Kazuyuki Kamegaki, Kenya Yamauchi, Yukinori Kitamura, Tuyoshi Nagase: Semiconductor integrated circuit device. Hitachi, Hitachi Microcomputer System, Hitachi Tobu Semiconductor, Hitachi Communication Systems Incorporated, Pennie & Edmonds, April 5, 1994: US05300798 (15 worldwide citation)

When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main exte ...


10
Nobuaki Kanazawa, Masao Mizukami, Kunihiro Ito: Differential type MOS transmission circuit. Hitachi, Hitachi Communication Systems, Fay Sharpe Beall Fagan Minnich & McKee, February 27, 1996: US05495186 (12 worldwide citation)

A differential type MOS transmission circuit includes a signal driving circuit and a signal receiving circuit to realize high speed transmission for a short distance transmission between different LSIs, etc. A pair of transmission lines between the signal driving circuit and the signal receiving cir ...