1
Randolph Mark, Hamilton Darlene, Kornitz Roni: Methods and systems for high write performance in multi-bit flash memory devices. Spansion, Randolph Mark, Hamilton Darlene, Kornitz Roni, DRAKE Paul S, November 10, 2005: WO/2005/106891 (6 worldwide citation)

Methods and circuits are presented for performing high speed write (programming) operations in a dual-bit flash memory array. The method (200) includes, for example, erasing (204) a first and second bit of each cell in the array to a first state, programming (206) the first bit of each cell in the a ...


2
Hamilton Darlene, Liu Zhizheng, Randolph Mark W, He Yi, Hsia Edward, Tanpairoj Kulachet, Lee Mimi, Madhani Alykhan: Memory device and method using positive gate stress to recover overerased cell. Advanced Micro Devices, Hamilton Darlene, Liu Zhizheng, Randolph Mark W, He Yi, Hsia Edward, Tanpairoj Kulachet, Lee Mimi, Madhani Alykhan, WRIGHT Hugh R, April 28, 2005: WO/2005/038815 (3 worldwide citation)

A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells (10) includes pre-programming (100) the plurality of memory cells (10), applying an erase pulse (110) to the plurality of memory cells (10) followed by an erase verification (12 ...


3
Hamilton Darlene, Bathul Fatima, Horiike Masato, Gershon Eugen, Vanbuskirk Michael A: Read approach for multi-level virtual ground memory. Spansion, Hamilton Darlene, Bathul Fatima, Horiike Masato, Gershon Eugen, Vanbuskirk Michael A, LAM Christine S, April 6, 2006: WO/2006/036783 (1 worldwide citation)

The present invention pertains to a technique (800) for determining the level of a bit in a dual sided ONO flash memory cell (500) where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels (540,542,544). One or more aspects of the present invention take into ...


4
Bathul Fatima, Hamilton Darlene, Horiike Masato: Multi-level ono flash program algorithm for threshold width control. Spansion, Bathul Fatima, Hamilton Darlene, Horiike Masato, LAM Christine S, July 20, 2006: WO/2006/076145 (1 worldwide citation)

Methods (400) of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages (300) are provided. The present invention employs an interactive program algorithm (400) that programs the bits of the wordline o ...


5
Hamilton Darlene G, Tanpairoj Kulachet, Hsia Edward, He Yi: Method of programming dual cell memory device to store multiple data states per cell. Advanced Micro Divices, Hamilton Darlene G, Tanpairoj Kulachet, Hsia Edward, He Yi, sCOLLOPY Daniel R, November 4, 2004: WO/2004/095469

A method of programming a multi-level, dual cell memory device (6). The method includes independently programming a first charge storing cell (38, 40) and a second charge storing cell (38, 40) to respective data states, the data states selected from a blank program level or one of a plurality of cha ...


6
Hamilton Darlene G, Tanpairoj Kulachet, Hsia Edward, Madhani Alykhan, Lee Mimi: Method of dual cell memory device operation for improved end-of-life read margin. Advanced Micro Devices, Hamilton Darlene G, Tanpairoj Kulachet, Hsia Edward, Madhani Alykhan, Lee Mimi, sCOLLOPY Daniel R, November 11, 2004: WO/2004/097837

A method of programming a dual cell memory device (6) having a first charge storing cell (38, 40) and a second charge storing cell (38, 40). According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage ...


7
Yang Nian, Ogawa Hiroyuki, Wu Yider, Chang Kuo Tung, Sun Yu, Hamilton Darlene G: Efficient use of wafer area with device under the pad approach. Spansion, Yang Nian, Ogawa Hiroyuki, Wu Yider, Chang Kuo Tung, Sun Yu, Hamilton Darlene G, sDRAKE Paul S, August 4, 2005: WO/2005/071749

More efficient use of silicon area is achieved by incorporating an active device (25) beneath a pad area (21) of a semiconductor structure (20). The pad area (21) includes a substrate (22) having a first metal layer (23) above it. A second metal layer (26) is below the first metal layer (23). The ac ...


8
Hsia Edward, Hamilton Darlene G, Shieh Ming Huei, Runnion Edward, Ajimine Eric, Chen Pau Ling, Randolph Mark W, He Yi: Improved method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array. Advanced Micro Devices, Hsia Edward, Hamilton Darlene G, Shieh Ming Huei, Runnion Edward, Ajimine Eric, Chen Pau Ling, Randolph Mark W, He Yi, sCOLLOPY Daniel R, August 19, 2004: WO/2004/070727

A method of storing a data pattern and reproducing the data pattern within an array 30 of memory cells 48, which includes active columns 45b and 45g and inactive (e.g. defective) columns 45c and 45f, comprises storing the data pattern within the active columns 45b and 45g. An inactive memory cell pr ...


9
Hsia Edward, Hamilton Darlene, Bathul Fatima, Horiike Masato: Erase algorithm multi-level bit flash memory. Spansion, Hsia Edward, Hamilton Darlene, Bathul Fatima, Horiike Masato, sDRAKE Paul S, January 5, 2006: WO/2006/001850

Methods (400) of erasing a sector of multi-level flash memory cells (MLB) having three or more data states (100, 200) to a single data state (1000) are provided. The present invention employs an interactive sector erase algorithm (400) that repeatedly erases (410, 440), verifies (416), soft programs ...


10
Kuo Tiao Hua, Leong Nancy, Yang Nian, Wang Guowei, Lee Aaron, Chandra Sachit, Vanbuskirk Michael A, Chen Johnny, Hamilton Darlene, Le Binh Quang: High performance flash memory device using a programming window for predetermination of bits to be programmed and DC-to-DC converter. Spansion, Kuo Tiao Hua, Leong Nancy, Yang Nian, Wang Guowei, Lee Aaron, Chandra Sachit, Vanbuskirk Michael A, Chen Johnny, Hamilton Darlene, Le Binh Quang, JAIPERSHAD Rajendra, March 29, 2007: WO/2007/035284

A method is provided for programming a nonvolatile memory array including an array (102) of memory cells (201), where each memory cell (201) including a substrate (310), a control gate (328), a charge storage element (322), a source region (203) and a drain region (202). The method includes receivin ...