1
Dr. Elke Erben
Dina Triyoso, Elke Erben, Klaus Hempel: Methods for fabricating integrated circuits with controlled P-channel threshold voltage. GLOBALFOUNDRIES, Ingrassia Fisher & Lorenz P C, April 16, 2013: US08420519 (3 worldwide citation)

Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the ...


2
Katherina Babich
Katherina E Babich, Alessandro C Callegari, Christopher D Sheraw, Eugene J O Sullivan: Filling narrow openings using ion beam etch. GLOBALFOUNDRIES, Williamson Morgan & Amerson P C, July 30, 2013: US08497212 (3 worldwide citation)

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes formi ...


3
Dr. Elke Erben
Sven Schmidbauer, Dina H Triyoso, Elke Erben, Hao Zhang, Robert Binder: Methods for fabricating integrated circuits with narrow, metal filled openings. GLOBALFOUNDRIES, Ingrassia Fisher & Lorenz P C, February 18, 2014: US08652890 (2 worldwide citation)

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high diele ...


4
Dr. Elke Erben
Elke Erben, Martin Trentzsch, Richard J Carter: Passivating point defects in high-K gate dielectric layers during gate stack formation. GLOBALFOUNDRIES, Amerson Law Firm PLLC, February 25, 2014: US08658490

Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material dep ...


5
Dr. Elke Erben
Dina Triyoso, Elke Erben, Robert Binder: Methods for fabricating integrated circuits with fluorine passivation. Globalfoundries, Ingrassia Fisher & Lorenz P C, July 29, 2014: US08791003

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluori ...


6
Katherina Babich
Katherina E Babich, Alessandro C Callegari, Christopher D Sheraw, Eugene J O Sullivan: Filling Narrow Openings Using Ion Beam Etch. Globalfoundries, August 30, 2012: US20120217590-A1

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes formi ...


7
Michael Hargrove, Richard J Carter, Ying H Tsang, George Kluth, Kisik Choi: Method of forming a semiconductor device. GLOBALFOUNDRIES, Ingrassia Fisher & Lorenz P C, November 1, 2011: US08048791 (103 worldwide citation)

Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel lay ...


8
Kaveri Mathur, James F Buller, Andreas Kurz: Semiconductor devices with improved local matching and end resistance of RX based resistors. Globalfoundries, Ditthavong Mori & Steiner P C, May 22, 2012: US08183107 (101 worldwide citation)

Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 keV, and at a relatively low implant ...


9
Itty Matthew, Bhanwar Singh: Process margin using discrete assist features. GLOBALFOUNDRIES, Turocy & Watson, July 6, 2010: US07749662 (90 worldwide citation)

The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometri ...


10
Benjamin Colombeau, Sai Hooi Yeong, Francis Benistant, Bangun Indajang, Lap Chan: Method for fabricating semiconductor devices with reduced junction diffusion. National University of Singapore, Globalfoundries Singapore, Horizon IP, November 8, 2011: US08053340 (79 worldwide citation)

A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are dispo ...