1
Satyen Mukherjee, Thomas Chang: Single transistor electrically programmable memory device and method. Exel Microelectronics, Limbach Limbach & Sutton, October 6, 1987: US04698787 (266 worldwide citation)

An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provi ...


2
Satyen Mukherjee, Thomas Chang: Single transistor electrically programmable memory device and method. Exel Microelectronics, Limbach Limbach & Sutton, September 19, 1989: US04868619 (65 worldwide citation)

An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provi ...


3
Thomas T L Chang, Chun Ho, Arun K Malhotra: Method for making electrically programmable memory device by doping the floating gate by implant. Exel Microelectronics, Limbach Limbach & Sutton, September 6, 1988: US04769340 (52 worldwide citation)

In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystallin ...


4
Erich Goetting: Security element circuit for programmable logic array. Exel Microelectronics Incorporated, Townsend and Townsend, March 14, 1989: US04812675 (28 worldwide citation)

An improved security circuit for a programmable logic array. One of the programmable elements of the array is designated as a security element, and its output is coupled to a latching mechanism. The output of the latching mechanism is coupled to a mechanism for disabling the read output of the array ...


5
Mukherjee Satyen, Chang Thomas: Single transistor electrically programmable device and method.. Exel Microelectronics, May 28, 1986: EP0182198-A2 (27 worldwide citation)

An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provi ...


6
Chang Thomas T L, Ho Chun, Malhotra Arun Kumar: An electrically programmable memory device and a method for making the same.. Exel Microelectronics, June 19, 1985: EP0144900-A2 (17 worldwide citation)

In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystallin ...


7
Erich Goetting: Field programmable matrix circuit for EEPROM logic cells. Exel Microelectronics, Townsend and Townsend, September 12, 1989: US04866432 (17 worldwide citation)

An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line ...


8
Cheen P Doung, Anil Gupta: Charge pump method and apparatus. Exel Microelectronics, Limbach Limbach & Sutton, May 19, 1987: US04667312 (16 worldwide citation)

A method and apparatus for transferring a signal from a high voltage, low current source to a word select line in an electrically erasable, programmable read-only memory wherein a control signal is generated which is incremented in magnitude over time, the control signal being used to control a sign ...


9
Goetting Erich: Security fuse circuit for programmable logic array.. Exel Microelectronics, October 19, 1988: EP0287338-A2 (10 worldwide citation)

One of the programmable elements of the array (20) is designated as a security element (22), and its output is coupled to a latching mechanism (30). The output of the latching mechanism (30) is coupled to a mechanism (36) for disabling the read output of the array (20). The latching mechanism (30) i ...


10
Bal S Sandhu: Power-up detector for low power systems. Exel Microelectronics, Limbach & Limbach L, July 14, 1998: US05781051 (7 worldwide citation)

A power-up reset detector circuit is described which uses the threshold voltages of NMOS and PMOS transistors to detect the power-up of integrated circuits, and uses a current mirror to track power supply and process variations.