1
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones: Enhanced DRAM with embedded registers. Enhanced Memory Systems, Peter J Meza, Michael R Casey, William J Kubida, March 23, 1999: US05887272 (59 worldwide citation)

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data ...


2
James Dean Joseph: Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM. Enhanced Memory Systems, William J Kubida Esq, Carol W Holland & Hart Burton Esq, February 23, 1999: US05875451 (36 worldwide citation)

A computer system with a hybrid main memory which includes both EDRAM and DRAM, with a DRAM cache provided within a designated portion of the EDRAM portion of the main memory. Read requests are handled by copying data being read from DRAM into a cache portion of EDRAM under the direction of a pseudo ...


3
David W Bondurant, Michael Peters, Kenneth J Mobley: Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank. Enhanced Memory Systems, William J Kubida Esq, Peter J Meza Esq, Kent Lembke Esq, December 11, 2001: US06330636 (28 worldwide citation)

A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventiona ...


4
Michael Alwais, Kenneth J Mobley: Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control. Enhanced Memory Systems, William J Holland & Hart Kubida Esq, November 23, 1999: US05991851 (20 worldwide citation)

An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memo ...


5
David Bondurant, David Fisch, Bruce Grieshaber, Kenneth Mobley, Michael Peters: Enhanced bus turnaround integrated circuit dynamic random access memory device. Enhanced Memory Systems, William J Kubida Esq, Carol W Hogan & Hartson Burton Esq, November 21, 2000: US06151236 (17 worldwide citation)

An enhanced bus turnaround integrated circuit dynamic random access memory ("DRAM") device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ("ZBT"), or pipeline burst sta ...


6
Kenneth J Mobley: Structure and method for hiding DRAM cycle time behind a burst access. Enhanced Memory Systems, William J Kubida Esq, Peter J Meza Esq, Hogan & Hartson, December 31, 2002: US06501698 (14 worldwide citation)

A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, d ...


7
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones: Enhanced DRAM with embedded registers. Enhanced Memory Systems, William J Kubida Esq, Hogan & Hartson, February 12, 2002: US06347357 (9 worldwide citation)

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data ...


8
Kenneth J Mobley: Multi-array memory device, and associated method, having shared decoder circuitry. Enhanced Memory Systems, William J Kubida Esq, May 16, 2000: US06064620 (9 worldwide citation)

A memory device, and an associated method, contains at least two memory arrays and a single decoder shared by the memory arrays. When data is to be accessed from selected memory locations of one of the memory arrays, the non-selected memory array is inactivated by precharging the bit lines of the ar ...


9
Michael Peters: Multi-bank ESDRAM with cross-coupled SRAM cache registers. Enhanced Memory Systems, Hogan & Hartson, June 19, 2001: US06249840 (5 worldwide citation)

A multi-bank ESDRAM, and an associated method, provides for the caching of data accessed from any DRAM memory array of the multi-bank ESDRAM device to any SRAM cache register of the ESDRAM device. Execution of a read operation is carried out using an existing command set utilized to read data from c ...


10
Kenneth J Mobley, Steve W Ash: Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements. Enhanced Memory Systems, William J Holland & Hart Kubida Esq, October 31, 2000: US06141281 (5 worldwide citation)

A technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable elements wherein each group of replaceable elements contains a circuit which enables an element group within a chained set to determine whether it is the "leftmost" (or first) e ...