1
Tushar R Gheewala, Robert J Lipp: Method and apparatus for sensing defects in integrated circuit elements. CrossCheck Technology, Townsend and Townsend, June 26, 1990: US04937826 (33 worldwide citation)

An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precha ...


2
Robert J Lipp: Method for operating a linear feedback shift register as a serial shift register with a crosscheck grid structure. CrossCheck Technology, Townsend and Townsend, December 4, 1990: US04975640 (25 worldwide citation)

A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck te ...


3
Tushar Gheewala: Method and apparatus for testing integrated circuits. Crosscheck Technology, Townsend and Townsend and Crew, February 27, 1996: US05495486 (21 worldwide citation)

Individual elements of an integrated circuit such as storage elements, (for example, latch elements), can be selectively coupled to select lines and probe lines. During normal operation the latches are not connected to the select lines and behave as a normal latch. During a write/control test operat ...


4
Tushar Gheewala, Rustam Mehta, Prab Varma: Storage element for delay testing. CrossCheck Technology, Townsend and Townsend and Crew, November 28, 1995: US05471152 (19 worldwide citation)

A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronize ...


5
Tushar R Gheewala: Method and apparatus for setting desired signal level on storage element. CrossCheck Technology, Townsend and Townsend, October 20, 1992: US05157627 (14 worldwide citation)

A desired signal level is set at select storage elements of an integrated circuit without relying on signals applied to the primary input pins of the integrated circuit. Instead, a signal is applied through a test matrix to the input, output or internal line of a select storage element. With the dri ...


6
Susheel J Chandra, Tushar Gheewala: Method and apparatus for locally deriving test signals from previous response signals. Crosscheck Technology, Townsend and Townsend Khourie and Crew, April 27, 1993: US05206862 (10 worldwide citation)

An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and ...


7
Kerry M Pierce, Thomas V Ferry: Method and apparatus for setting desired logic state at internal point of a select storage element. CrossCheck Technology, Townsend and Townsend, January 12, 1993: US05179534 (10 worldwide citation)

An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal tran ...


8
Susheel J Chandra, Tushar Gheewala: Method for testing a sequential circuit by splicing test vectors into sequential test pattern. CrossCheck Technology, Townsend and Townsend Khourie and Crew, July 20, 1993: US05230001 (8 worldwide citation)

During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To tes ...


9
Tushar Gheewala, Rustam Mehta, Timothy Saxe: Method and structure for routing power for optimum cell utilization with two and three level metal in a partially predesigned integrated circuit. CrossCheck Technology, Townsend and Townsend Khourie and Crew, July 25, 1995: US05436801 (1 worldwide citation)

An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlyi ...


10
Lipp Robert J: Method for operating a linear feedback shift register as a serial shift register with a crosscheck grid.. Crosscheck Technology A de, August 28, 1991: EP0443081-A2

A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck te ...