1
Eb Eshun
Coolbaugh Douglas D, Eshun Ebenezer E, Feilchenfeld Natalie, Gautsch Michael L, He Zhong Xiang, Moon Matthew D, Ramachandran Vidhya, Waterhouse Barbara: Formation of metal-insulator metal capacitor using a hardmask. International Business Machines Corporation, Coolbaugh Douglas D, Eshun Ebenezer E, Feilchenfeld Natalie, Gautsch Michael L, He Zhong Xiang, Moon Matthew D, Ramachandran Vidhya, Waterhouse Barbara, CANALE Anthony J, December 22, 2005: WO/2005/122245

Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) ab ...


2
Eb Eshun
Coolbaugh Douglas D, Eshun Ebenezer E, Gambino Jeffrey P, He Zhong Xiang, Ramachandran Vidhya: Metal-insulator-metal capacitor and method of fabrication. International Business Machines Corporation, Coolbaugh Douglas D, Eshun Ebenezer E, Gambino Jeffrey P, He Zhong Xiang, Ramachandran Vidhya, SABO William D, April 14, 2005: WO/2005/034201

A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top su ...


3
Coolbaugh Douglas D, Greer Heidi L, Rassel Robert M: Precision polysilicon resistor process. International Business Machines Corporation, Coolbaugh Douglas D, Greer Heidi L, Rassel Robert M, SABO William D, April 14, 2005: WO/2005/034202

A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter / FET activation rapid thermal anneal (RTA) on a wafer having partial ...


4
Coolbaugh Douglas D, Downes Keith E, Lindgren Peter J, Stamper Anthony K: Dual-damascene process to fabricate thick wire structure. International Business Machines Corporation, Coolbaugh Douglas D, Downes Keith E, Lindgren Peter J, Stamper Anthony K, SABO William D, July 26, 2007: WO/2007/084982

A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least o ...


5
Coolbaugh Douglas D, Furkay Stephen S, Johnson Jeffrey B, Rassel Robert M: Method for forming a one mask hyperabrupt junction varactor using a compensated cathode contact. International Business Machines Corporation, Coolbaugh Douglas D, Furkay Stephen S, Johnson Jeffrey B, Rassel Robert M, SABO William D, July 13, 2006: WO/2006/073943

A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.


6
Chinthakindi Anil K, Coolbaugh Douglas D, Ramachandran Vidhya, Rassel Robert M: Feol/meol metal resistor for high end cmos. International Business Machines Corporation, Chinthakindi Anil K, Coolbaugh Douglas D, Ramachandran Vidhya, Rassel Robert M, SABO William D, February 16, 2006: WO/2006/017600

A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of ...


7
Coolbaugh Douglas D, Hershberger Douglas B, Rassel Robert M: Mos varactor using isolation well. International Business Machines Corporation, Coolbaugh Douglas D, Hershberger Douglas B, Rassel Robert M, SABO William D, March 9, 2006: WO/2006/026055

The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing sch ...



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