1
Sik On Kong: Three dimensional IC package module. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, March 25, 2003: US06538333 (238 worldwide citation)

In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling ...


2
Igor V Peidous: Shallow trench isolation of MOSFETS with reduced corner parasitic currents. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, November 23, 1999: US05989978 (206 worldwide citation)

A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which rounds off the corners and also reduces the effect of tensile stresses caused by the densified trench ...


3
Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah: Method of manufacturing semiconductor local interconnect and contact. Chartered Semiconductor Manufacturing, Mikio Ishimaru, April 26, 2005: US06884712 (174 worldwide citation)

An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped sp ...


4
Cher Liang Cha, Alex See, Lap Chan: Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, October 16, 2001: US06303418 (166 worldwide citation)

A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator ...


5
Shyue Fong Quek, Ying Keung Leung, Sang Yee Loong, Ting Cheong Ang: Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, December 10, 2002: US06492726 (155 worldwide citation)

In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package a ...


6
Peter Chew: Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer. Chartered Semiconductor Manufacturing, George O Saile, Stephen B Ackerman, Alek P Szecsy, January 12, 1999: US05858876 (151 worldwide citation)

A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer ...


7
Su Ping Teong: Etch stop for copper damascene process. Chartered Semiconductor Manufacturing, George O Saile, Stephen B Ackerman, December 2, 1997: US05693563 (141 worldwide citation)

The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is ...


8
Vladislav Vassiliev: Method of silicon oxide and silicon glass films deposition. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, William J Stoffel, March 6, 2001: US06197705 (130 worldwide citation)

A method for fabricating a silicon oxide and silicon glass layers at low temperature using soft power-optimized Plasma-Activated CVD with a TEOS-ozone-oxygen reaction gas mixture (TEOS O


9
Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek: Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, Stephen G Stanton, October 9, 2001: US06300177 (127 worldwide citation)

A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a por ...


10
Lap Chan, Hou Tee Ng: Method for planarized interconnect vias using electroless plating and CMP. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, October 24, 2000: US06136693 (121 worldwide citation)

An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating ...



Click the thumbnails below to visualize the patent trend.