1
Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Bingham McCutchen, June 3, 2008: US07383521 (282 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


2
Robert C Pack, Louis K Scheffer: Method and system for context-specific mask inspection. Cadence Design Systems, Bingham McCutchen, June 12, 2007: US07231628 (258 worldwide citation)

A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.


3
David White, Taber H Smith: Adjustment of masks for integrated circuit fabrication. Cadence Design Systems, Bingham McCutchen, April 29, 2008: US07367008 (211 worldwide citation)

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch pro ...


4
Taber H Smith, Vikas Mehrotra, David White: Use of models in integrated circuit fabrication. Cadence Design Systems, Bingham McCutchen, April 15, 2008: US07360179 (199 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


5
Ravi Varadarajan, Robert Thompson: Optimized placement and routing of datapaths. Cadence Design Systems, Fenwick & West, November 17, 1998: US05838583 (199 worldwide citation)

A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing ...


6
Harish Kriplani, Shiang Tang Huang: Systems, methods, and apparatus to perform statistical static timing analysis. Cadence Design Systems, Alford Law Group, William Alford, Teresa Wong, February 3, 2009: US07487475 (198 worldwide citation)

A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and ...


7
Etienne Jacques, Tom Kronmiller: Removal of acute angles in a design layout. Cadence Design Systems, Stattler Johnson & Adeli, June 20, 2006: US07065731 (180 worldwide citation)

Some embodiments of the invention provide novel methods for removing acute angles form routes in a design layout. The method reacts a route with several segments. It then identifies an acute angle between first and second contiguous segments of the route. The method next inserts a third segment betw ...


8
Abdurrahman Sezginer, Roy Prasad: Apparatus and method for breaking up and merging polygons. Cadence Design Systems, Sheppard Mullin Richter & Hampton, March 17, 2009: US07506300 (180 worldwide citation)

A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in th ...


9
David White, Taber H Smith: Characterization and verification for integrated circuit designs. Cadence Design Systems, Vista IP Law Group, May 4, 2010: US07712056 (162 worldwide citation)

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process ...


10
David White, Taber H Smith: Electronic design for integrated circuits based on process related variations. Cadence Design Systems, Vista IP Law Group, June 14, 2011: US07962867 (161 worldwide citation)

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on ...