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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (12 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


2
Bill Colin S, Cai Wei Daisy: Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices. Spansion, Bill Colin S, Cai Wei Daisy, JAIPERSHAD Rajendra, December 7, 2006: WO/2006/130438 (10 worldwide citation)

In the present method of programming and erasing the resistive memory devices (30) of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices (30) whose state is to be changed from the previous state the ...


3
Bill Colin S, Cai Wei Daisy: Temperature compensation of thin film diode voltage threshold in memory sensing circuit. Spansion, Bill Colin S, Cai Wei Daisy, DRAKE Paul S, September 28, 2006: WO/2006/102391 (7 worldwide citation)

Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) ca ...


4
Lan Zhida, Van, Buskirk Michael A, Bill Colin S: Memory device and methods of using and making the device. Advanced Micro Devices, Lan Zhida, Van, Buskirk Michael A, Bill Colin S, sCOLLOPY Daniel R, February 3, 2005: WO/2005/011014 (3 worldwide citation)

A memory cell (104) made of two electrodes(106, 202, 108, 204) with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media (110) contains an active low conductive layer (112) and passive layer (114). The controllably conductive media (110) changes ...


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Fang Tzu Ning, Vanbuskirk Michael A, Bill Colin S: Control of memory devices possessing variable resistance characteristics. Advanced Micro Devices, Fang Tzu Ning, Vanbuskirk Michael A, Bill Colin S, DRAKE Paul S, April 6, 2006: WO/2006/036622 (3 worldwide citation)

Systems and methods employing at least one constant current source (114, 404) to facilitate programming of an organic memory cell (102, 302, 402, 904, 1102, 1206) and/or employing at least one constant voltage source (112, 304) to facilitate erasing of a memory device (200, 300, 400, 900, 1100). The ...


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Vanbuskirk Michael A, Bill Colin S, Lan Zhida, Fang Tzu Ning: Write-once read-many times memory. Spansion, Vanbuskirk Michael A, Bill Colin S, Lan Zhida, Fang Tzu Ning, DRAKE Paul S, October 5, 2006: WO/2006/104858 (2 worldwide citation)

A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a cha ...


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Bill Colin S, Kaza Swaroop, Fang Tzu Ning, Spitzer Stuart: Method of programming, reading and erasing memory-diode in a memory-diode array. Spansion, Bill Colin S, Kaza Swaroop, Fang Tzu Ning, Spitzer Stuart, LAM Christine S, July 6, 2006: WO/2006/071683 (1 worldwide citation)

A memory array (140) includes first and second sets of conductors (142), (144) and a plurality of memory-diodes (130), each connecting in a forward direction a conductor (BL) of the first set (142) with a conductor (WL) of the second set (144). An electrical potential is applied across a selected me ...


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Bill Colin S, Vanbuskirk Michael A, Lan Zhida, Ennals John S, Fang Tzu Ning: Polymer-based transistor devices, methods, and systems. Advanced Micro Devices, Bill Colin S, Vanbuskirk Michael A, Lan Zhida, Ennals John S, Fang Tzu Ning, DRAKE Paul S, June 7, 2007: WO/2007/064334

Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and contain ...


9
Bill Colin S, Vanbuskirk Michael A: Vertical jfet as used for selective component in a memory array. Spansion, Bill Colin S, Vanbuskirk Michael A, LAM Christine S, March 16, 2006: WO/2006/029280

Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell (602) in a memory array while increasing device density in the memory cell array. A vertical JFET (400, 500, 604, 700, 800, 900) is described to which voltages can be selectively applied to ...


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Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene: Program/erase waveshaping control to increase data retention of a memory cell. Spansion, Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene, JAIPERSHAD Rajendra, February 8, 2007: WO/2007/015864

System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across ...