1
Rubil Ahmadi: Sense amplifier based flip-flop. ATI Technologies ULC, Vedder Price P C, April 6, 2010: US07692466 (114 worldwide citation)

A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signa ...


2
Mark M Leather, Eric Demers: Parallel pipeline graphics system. ATI Technologies ULC, Vedder Price P C, December 15, 2009: US07633506 (69 worldwide citation)

The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on scre ...


3
Roden R Topacio, Vincent Chan, Fan Yeung: Semiconductor chip bump connection apparatus and method. ATI Technologies ULC, Timothy M Honeycutt, March 2, 2010: US07670939 (51 worldwide citation)

Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and posi ...


4
John S Yates Jr, Matthew F Storch, Sandeep Nijhawan, Dale R Jurich, Korbin S Van Dyke: Apparatus for executing programs for a first computer architechture on a computer of a second architechture. ATI Technologies ULC, Volpe and Koenig P C, February 28, 2012: US08127121 (48 worldwide citation)

Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing ...


5
Gordon F Caruk, Carrell R Killebrew Jr: Method and apparatus for managing power consumption relating to a differential serial communication link. ATI Technologies ULC, Vedder Price P C, January 20, 2009: US07480808 (37 worldwide citation)

Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal oper ...


6
John S Yates Jr, David L Reese, Korbin S Van Dyke, Tiruvur R Ramesh, Paul H Hohensee: Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code. ATI Technologies ULC, Volpe and Koenig P C, December 6, 2011: US08074055 (35 worldwide citation)

A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into ...


7
Sasa Marinkovic, Phil Mummah, Mingwei Chien, Michael Tresidder, Roumen Saltchev, George Xie, Jason Long: Device having multiple graphics subsystems and reduced power consumption mode, software and methods. ATI Technologies ULC, Vedder Price P C, June 1, 2010: US07730336 (34 worldwide citation)

Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphi ...


8
John S Yates Jr, David L Reese, Paul H Hohensee, Stephen C Purcell, Korbin S Van Dyke: Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions. ATI Technologies ULC, Volpe and Koenig P C, February 21, 2012: US08121828 (32 worldwide citation)

A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a quer ...


9
Marinkovic Sasa, Saltchev Roumen, Xie George, Mummah Phil, Chien Mingwei, Long Jason, Tresidder Michael: Device having multiple graphics subsystems and reduced power consumption mode, software and methods. Ati Technologies Ulc, Marinkovic Sasa, Saltchev Roumen, Xie George, Mummah Phil, Chien Mingwei, Long Jason, Tresidder Michael, RECKAMP Christopher J, December 6, 2007: WO/2007/140404 (25 worldwide citation)

Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphi ...


10
James L Esliger: Power source dependent program execution. ATI Technologies ULC, Vedder Price P C, May 11, 2010: US07716500 (24 worldwide citation)

An electronic device having a processor powered by a power source may be operated by providing a plurality of program portions individually executable by the processor for performing the same computing function. Each program portion causes the processor to exhibit a different instantaneous power con ...