1
John S Yates Jr, David L Reese, Korbin S Van Dyke: Recording in a program execution profile references to a memory-mapped active device. ATI International, David E Boundy Esq, Schulte Roth & Zabel, May 28, 2002: US06397379 (191 worldwide citation)

A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instr ...


2
Korbin S Van Dyke: Method and apparatus for restricting memory access. ATI International S R L, Vedder Price Kaufman & Kammholz, November 20, 2001: US06321314 (183 worldwide citation)

A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the proc ...


3
David E Sinclair, Eric Young: Dynamic graphics and/or video memory power reducing circuit and method. ATI International, Vedder Price Kaufman & Kammholz P C, December 2, 2003: US06657634 (161 worldwide citation)

An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requ ...


4
Korbin S Van Dyke, Paul Campbell, Don Alan Van Dyke: Computer for execution of RISC and CISC instruction sets. ATI International, David E Boundy, Willkie Farr & Gallagher, May 16, 2006: US07047394 (142 worldwide citation)

A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instruction ...


5
John S Yates, David L Reese, Korbin S Van Dyke: Detecting modification to computer memory by a DMA device. ATI International, Joel E Lutzker, David E Boundy, Schulte Roth & Zabel, April 15, 2003: US06549959 (141 worldwide citation)

A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided ...


6
James P Duhault: Method and apparatus for displaying video in a data processing system. ATI International, Vedder Price Kaufman & Kammholz, September 24, 2002: US06456334 (121 worldwide citation)

In one embodiment of the present invention, a plurality of video images are displayed on a scalable window associated with a computer device. One of the first portion of the plurality of images is updated by a first tuner, a second portion of the plurality of images is updated by a second tuner. By ...


7
John S Yates Jr, David L Reese, Korbin S Van Dyke: Recording classification of instructions executed by a computer. ATI International, David E Boundy, Willkie Farr & Gallagher, October 11, 2005: US06954923 (113 worldwide citation)

An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instruction ...


8
Korbin S Van Dyke, Paul H Hohensee, David L Reese, John S Yates Jr, T R Ramesh, Shalesh Thusoo, Gurjeet Singh Saund, Stephen C Purcell, Niteen Aravind Patkar: Profiling execution of computer programs. ATI International, David E Boundy, Willkie Farr & Gallagher, March 14, 2006: US07013456 (113 worldwide citation)

A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with th ...


9
Stephen L Morein, Andrew E Gruber: Method and apparatus for graphics processing using parallel graphics processors. ATI International, Vedder Price Kaufman & Kammholz, October 29, 2002: US06473086 (105 worldwide citation)

A method and apparatus for graphics processing that utilizes multiple graphics processors in parallel is presented. A primary graphics processor is operably coupled to a primary memory that includes a primary color buffer and a primary Z buffer. The primary processor processes a first portion of the ...


10
Allen J C Porter: Method and apparatus for displaying multiple graphics images in a mixed video graphics display. ATI International, Markison & Reckamp P C, March 27, 2001: US06208354 (102 worldwide citation)

A method and apparatus for storing and displaying multiple graphical images in a mixed video and graphics display is accomplished by determining an amount of memory sufficient to display a single graphics image in a subset of the display. Once the amount of memory required for a single image is dete ...