1
Meng Bing Yu, Era K Nangia, Michael Ni, Vidya Rajagopalan: Data cache virtual hint way prediction, and applications thereof. ARM Finance Overseas, Patterson Thuente Pedersen P A, July 28, 2015: US09092343 (7 worldwide citation)

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is ava ...


2
Robert Gelinas, W Patrick Hays, Sol Katzman, William J Dally: Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities. ARM Finance Overseas, Patterson Thuente Pedersen P A, June 2, 2015: US09047093 (2 worldwide citation)

Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for ...


3
Kevin D Kissell: Virtual machine coprocessor for accelerating software execution. ARM FINANCE OVERSEAS, Patterson Thuente Pedersen P A, December 8, 2015: US09207958 (1 worldwide citation)

In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a proc ...


4
David Yiu Man Lau: Merged floating point operation using a modebit. Arm Finance Overseas, Patterson Thuente Pedersen P A, December 30, 2014: US08924454 (1 worldwide citation)

A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit rece ...


5
Meng Bing Yu, Era K Nangia, Michael Ni: Load/store unit for a processor, and applications thereof. ARM Finance Overseas, Patterson Thuente Pedersen P A, April 17, 2018: US09946547

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. W ...


6
Meng Bing Yu, Era K Nangia, Michael Ni, Karagada Ramarao Kishore: Data cache virtual hint way prediction, and applications thereof. ARM Finance Overseas, Patterson Thuente Pedersen P A, April 25, 2017: US09632939

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is ava ...


7
Kjeld Svendsen: Compact linked-list-based multi-threaded instruction graduation buffer. ARM Finance Overseas, Patterson Thuente Pedersen P A, December 26, 2017: US09851975

A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values ...


8
William Lee, Thomas Benjamin Berg: Speculative read in a cache coherent microprocessor. ARM Finance Overseas, Patterson Thuente Pedersen P A, September 22, 2015: US09141545

A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the s ...


9
Robert Gelinas, W Patrick Hays, Sol Katzman, William J Dally: Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated. ARM Finance Overseas, Patterson Thuente Pedersen P A, December 13, 2016: US09519507

Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for ...


10
Kevin D Kissell: Virtual machine coprocessor for accelerating software execution. ARM Finance Overseas, Patterson Thuente Pedersen P A, August 21, 2018: US10055237

In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a proc ...