1
Ashley Miles Stevens: Peripheral buses for integrated circuit. Arm, Nixon & Vanderhye P C, May 16, 2000: US06064626 (88 worldwide citation)

The present invention provides an integrated circuit comprising a system bus to which a processor is connectable, and first and second peripheral buses to which peripheral units used by said processor are connected, the first peripheral bus operating at a higher clock speed than the second periphera ...


2
Emre Özer, Stuart David Biles, Simon Andrew Ford: Managing cache coherency in a data processing apparatus. ARM, Nixon & Vanderhye P C, May 3, 2011: US07937535 (83 worldwide citation)

Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the da ...


3
Richard York, David James Seal, Dominic Hugo Symes: Coprocessor data access control. Arm, Nixon & Vanderhye PC, December 14, 1999: US06002881 (64 worldwide citation)

A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only control ...


4
Andrew Mark Nightingale: Testing compliance of a device with a bus protocol. Arm, Nixon & Vanderhye P C, April 5, 2005: US06876941 (63 worldwide citation)

The present invention provides a system and method for testing compliance of a device with a bus protocol. The method comprises the steps of reading a configuration file containing predetermined parameters identifying the type of device and capabilities of the device, and then employing a configurat ...


5
David Vivian Jaggar, William Adam Hohl: Executing debug instructions. Arm, Nixon & Vanderhye P C, November 20, 2001: US06321329 (59 worldwide citation)

Apparatus for processing data is provided, said apparatus comprising: a main processor


6
Martin San Juan: Apparatus and method for testing master logic units within a data processing apparatus. ARM, Nixon & Vanderhye P C, October 8, 2002: US06463488 (59 worldwide citation)

The present invention provides a data processing apparatus and method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units for accessing a bus in order to initiate processing requests, and a test controller for tes ...


7
Michael John Williams, Paul Kimelman, Jon Andrew Rijk: Breakpoint logic unit, debug logic and breakpoint method for a data processing apparatus. ARM, Nixon & Vanderhye P C, February 19, 2008: US07334161 (56 worldwide citation)

The present invention provides a breakpoint logic unit, debug logic and breakpoint method for a data processing apparatus. The breakpoint logic unit comprises a value storage operable to store data indicative of a selected value for an operational characteristic of the data processing apparatus, and ...


8
David Vivian Jaggar: Coprocessor opcode division by data type. Arm, Nixon & Vanderhye P C, June 12, 2001: US06247113 (54 worldwide citation)

A data processing system having a main processor and a coprocessor. The main processor responsds to coprocessor instructions within its instruction stream by issuing the coprocessor instructions upon a coprocessor bus and detecting if the coprocessor accepts them by returning an accept signal. The c ...


9
Andrew Brookfield Swaine, David James Williamson: Tracing multiple data access instructions. ARM, Nixon & Vanderhye P C, July 18, 2006: US07080289 (48 worldwide citation)

A microprocessor integrated circuit 104 is provided with a trace controller 120 that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller 120 is ...


10
Donald Felton: Security provision for a subject image displayed in a non-secure domain. ARM, Nixon & Vanderhye P C, April 22, 2014: US08707056 (48 worldwide citation)

A data processing device is provided with a processor core 8 that can operate in either a secure domain or a non-secure domain. Data stored within a secure region 34 of a memory 10 can only be accessed when the processor core 8 is executing in the secure domain. A frame buffer 36 for storing a displ ...