61
Michael K Templeton, Ramkumar Subramanian, Bharath Rangarajan, Kathleen R Early, Ursula Q Quinto: Chemical feature doubling process. Advanced Micro Devices, Amin & Turocy, March 18, 2003: US06534243 (155 worldwide citation)

In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least o ...


62
Matthew S Buynoski, Judy Xilin An, Haihong Wang, Bin Yu: Double spacer FinFET formation. Advanced Micro Devices, Harrity & Snyder, March 23, 2004: US06709982 (155 worldwide citation)

A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the ox ...


63
Takao Akaogi, Lee Edward Cleveland, Kendra Nguyen: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, Brinks Hofer Gilson & Lione, May 29, 2001: US06240040 (154 worldwide citation)

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


64
Agrawal Om Prakash, Wright Michael James, Shen Ju: Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.. Advanced Micro Devices, March 6, 1991: EP0415542-A2 (152 worldwide citation)

A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic bl ...


65
Qi Xiang, Scott Allan Bell, Chih Yuh Yang: Process for fabricating a semiconductor device component using a selective silicidation reaction. Advanced Micro Devices, Brinks Hofer Gilson & Lione, April 3, 2001: US06211044 (151 worldwide citation)

A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reacting a reaction lay ...


66
David S Christie: Chipset configured to perform data-directed prefetching. Advanced Micro Devices, Lawrence J Merkel, Conley Rose & Tayon PC, June 12, 2001: US06247107 (150 worldwide citation)

A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated by the processors to the main memory, and returns the data provided therefrom to the processors. Addit ...


67
Shane Hollmer, Pau Ling Chen: Auto adjusting window placement scheme for an NROM virtual ground array. Advanced Micro Devices, Brinks Hofer Gilson & Lione, April 24, 2001: US06222768 (150 worldwide citation)

A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. The threshold voltages of the memory elements gradually increase over operating cycles due to trapping of charge in the nitride or oxide, eve ...


68
Candice H Brown: Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom. Advanced Micro Devices, Patrick T King, John P Taylor, Eugene H Valet, March 1, 1988: US04729061 (150 worldwide citation)

The invention discloses an improved PC board package for at least one integrated circuit die utilizing a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The ...


69
Lee E Cleveland, Michael A Van Buskirk, Johhny C Chen, Chung K Chang: Independent array grounds for flash EEPROM array with paged erase architechture. Advanced Micro Devices, Davis Chin, November 15, 1994: US05365484 (150 worldwide citation)

An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generatin ...


70
Kouros Ghandehari, Jean Y Yang, Christopher A Spence: Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types. Advanced Micro Devices, Mikio Ishimaru, February 7, 2006: US06994939 (149 worldwide citation)

A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the ...



Click the thumbnails below to visualize the patent trend.