51
Unsoon Kim, Hung Sheng Chen, Kashmir Sahota, Yu Sun: Core array and periphery isolation technique. Advanced Micro Devices, Foley & Lardner, December 21, 1999: US06004862 (165 worldwide citation)

A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semico ...


52
David B Witt, Rajiv M Hattangadi: Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates. Advanced Micro Devices, B Noel Kivlin, Lawrence J Merkel, Conley Rose & Tayon PC, January 12, 1999: US05860104 (164 worldwide citation)

A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for th ...


53
Sergey D Lopatin, Carl Galewski, Takeshi T N Nogami: Method of copper interconnect formation using atomic layer copper deposition. Advanced Micro Devices, Genus, LaRiviere Grubman & Payne, April 9, 2002: US06368954 (164 worldwide citation)

A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic l ...


54
Bin Yu: Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology. Advanced Micro Devices, Monica H Choi, May 13, 2003: US06562665 (164 worldwide citation)

For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top ...


55
Richard J Huang, Philip A Fisher, Cyrus E Tabery: Use of diamond as a hard mask material. Advanced Micro Devices, Foley & Lardner, January 6, 2004: US06673684 (164 worldwide citation)

A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portio ...


56
Anthony John Toprac, Douglas John Downey, Subhash Gupta: Run-to-run control process for controlling critical dimensions. Advanced Micro Devices, Ken J Koestner, Skjerven Morrill MacPherson Franklin & Friel, July 20, 1999: US05926690 (163 worldwide citation)

It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedbac ...


57
Robert Alan Williams, Mohan Kalkunte: Apparatus and method for selectively controlling transmission of consecutive packets in a network station. Advanced Micro Devices, April 25, 2000: US06055578 (162 worldwide citation)

Delay times are modified in an Ethernet network device having captured the media channel by increasing the interframe spacing (IFS) between data packets. The modified IFS interval, increased by adding a delay interval to the minimum interpacket gap (IPG) interval after a first user-selectable number ...


58
Takeshi Nogami, Sergey Lopatin, Young Chang Joo: Method of forming copper/copper alloy interconnection with reduced electromigration. Advanced Micro Devices, June 5, 2001: US06242349 (161 worldwide citation)

The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to a ...


59
Srikanteswara Dakshina Murthy, Chih Yuh Yang, Bin Yu: Epitaxially grown fin for FinFET. Advanced Micro Devices, Harrity & Snyder, December 28, 2004: US06835618 (160 worldwide citation)

A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method further includes growing a second material in the trench to form ...


60
Zhigang Wang, Xin Guo, Yue Song He: Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling. Advanced Micro Devices, Renner Otto Boisselle & Sklar, September 9, 2003: US06617639 (156 worldwide citation)

A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control ...



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