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Bin Yu, Eric N Paton: MOSFET having a double gate. Advanced Micro Devices, Renner Otto Boisselle & Sklar, November 11, 2003: US06646307 (192 worldwide citation)

A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electro ...


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Daniel Mann: Processor having a trace access instruction to access on-chip trace memory. Advanced Micro Devices, Zagorin O&apos Brien & Graham, November 6, 2001: US06314530 (185 worldwide citation)

A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory ...


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Qingsu Wang, Gerald Barnett, R Michael Greig, Yi Cheng: System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, January 12, 1999: US05859964 (175 worldwide citation)

A system and method for detecting faults in wafer fabrication process tools by acquiring real-time process parameter signal data samples used to model the process performed by the process tool. The system includes a computer system including a DAQ device, which acquires the data samples, and a fault ...


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Narbeh Derhacobian, Hao Fang: Method for reducing program disturb during self-boosting in a NAND flash memory. Advanced Micro Devices, November 23, 1999: US05991202 (174 worldwide citation)

A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a pl ...


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Angela T Hui, Bhanwar Singh: Method of forming smaller contact size using a spacer hard mask. Advanced Micro Devices, Foley & Lardner, February 4, 2003: US06514849 (174 worldwide citation)

An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sid ...


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Pankaj Dixit, Jack Sliwa, Richard K Klein, Craig S Sander, Mohammad Farnaam: Contact plug and interconnect employing a barrier lining and a backfilled conductor material. Advanced Micro Devices, Ashen Golant Martin & Seldon, November 28, 1989: US04884123 (172 worldwide citation)

A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion an ...


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Mohan Kalkunte, Jayant Kadambi, Shashank Merchant: Apparatus and method in a network switch for dynamically allocating bandwidth in ethernet workgroup switches. Advanced Micro Devices, August 22, 2000: US06108306 (171 worldwide citation)

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to IEEE 802.3 protocol dynamically allocates bandwidth between the switch ports based upon detected activity from the network nodes. The network switch generates an assigned ban ...


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William George En, Angela Hui, Minh Van Ngo: Methods for improving carrier mobility of PMOS and NMOS devices. Advanced Micro Devices, Eschweiler & Associates, June 3, 2003: US06573172 (171 worldwide citation)

Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in ...


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Ming Ren Lin, Jung Suk Goo, Haihong Wang, Qi Xiang: FinFET device incorporating strained silicon in the channel region. Advanced Micro Devices, Foley & Lardner, October 5, 2004: US06800910 (171 worldwide citation)

A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epi ...



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