21
Valery Dubin, Chiu Ting: Method for fabricating copper-aluminum metallization. Advanced Micro Devices, Edward C Kwok, Skjerven Morrill MacPherson Franklin & Friel, June 15, 1999: US05913147 (213 worldwide citation)

A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.


22
Bernard J New: Bit slice microprogrammable processor for signal processing applications. Advanced Micro Devices, Gary T Aka, J Ronald Richbourg, July 12, 1983: US04393468 (212 worldwide citation)

A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connec ...


23
Pau Ling Chen, Michael S C Chung, Shane C Hollmer, Vincent Leung, Binh Quang Le, Masaru Yano: Scheme for page erase and erase verify in a non-volatile memory array. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, November 30, 1999: US05995417 (208 worldwide citation)

A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a ...


24
Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina Murthy, Haihong Wang, Bin Yu: Narrow fin FinFET. Advanced Micro Devices, Harrity & Snyder, July 26, 2005: US06921963 (207 worldwide citation)

A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.


25
Colin S Bill, Sameer S Haddad: Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells. Advanced Micro Devices, Davis Chin, January 27, 1998: US05712815 (203 worldwide citation)

An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selecte ...


26
Richard J Huang, Angela Hui, Robin Cheung, Mark Chang, Ming Ren Lin: Simplified dual damascene process for multi-level metallization and interconnection structure. Advanced Micro Devices, June 3, 1997: US05635423 (199 worldwide citation)

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer thereb ...


27
Luigi Capodieci: Modification of mask layout data to improve writeability of OPC. Advanced Micro Devices, Amin Eschweiler & Turocy, March 28, 2000: US06044007 (197 worldwide citation)

A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner ...


28
Vincent Cheekiat Lim, Preetham Raghuvanshi: Power save management with customized range for user configuration and tuning value based upon recent usage. Advanced Micro Devices, Hamilton & Terrile, Michael Rocco Cannatti, March 17, 2009: US07505795 (193 worldwide citation)

A method and system for efficiently managing power consumption in a mobile device controls power consumption with an adjustable sleep period or listening interval that may be user-specified and automatically tuned based on recent detected usage. With an adjustable sleep period, a receiver conserves ...


29
Donald L Wollesen: High conductivity interconnection line. Advanced Micro Devices, Lowe Price LeBlanc & Becker, August 19, 1997: US05659201 (193 worldwide citation)

High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above th ...


30
Nicholas A Schmitz: Apparatus and method for allocation of resoures in programmable logic devices. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, July 7, 1992: US05128871 (193 worldwide citation)

Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation mea ...



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