Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina Murthy, Haihong Wang, Bin Yu: Narrow fin FinFET. Advanced Micro Devices, Harrity & Snyder, July 26, 2005: US06921963 (219 worldwide citation)

A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Antonio J Montalvo, Michael A Van Buskirk: Flash EEPROM array with paged erase architecture. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, June 30, 1992: US05126808 (218 worldwide citation)

A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means fo ...

Sameer S Haddad, Chi Chang, Antonio Matalvo, Michael A Van Buskirk: Flash EEPROM array with negative gate voltage erase operation. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, December 31, 1991: US05077691 (218 worldwide citation)

A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed ...

Bernard J New: Bit slice microprogrammable processor for signal processing applications. Advanced Micro Devices, Gary T Aka, J Ronald Richbourg, July 12, 1983: US04393468 (213 worldwide citation)

A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connec ...

Bin Yu, Eric N Paton: MOSFET having a double gate. Advanced Micro Devices, Renner Otto Boisselle & Sklar, November 11, 2003: US06646307 (213 worldwide citation)

A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electro ...

Pau Ling Chen, Michael S C Chung, Shane C Hollmer, Vincent Leung, Binh Quang Le, Masaru Yano: Scheme for page erase and erase verify in a non-volatile memory array. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, November 30, 1999: US05995417 (209 worldwide citation)

A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a ...

Luigi Capodieci: Modification of mask layout data to improve writeability of OPC. Advanced Micro Devices, Amin Eschweiler & Turocy, March 28, 2000: US06044007 (205 worldwide citation)

A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner ...

Colin S Bill, Sameer S Haddad: Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells. Advanced Micro Devices, Davis Chin, January 27, 1998: US05712815 (204 worldwide citation)

An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selecte ...

Richard J Huang, Angela Hui, Robin Cheung, Mark Chang, Ming Ren Lin: Simplified dual damascene process for multi-level metallization and interconnection structure. Advanced Micro Devices, June 3, 1997: US05635423 (199 worldwide citation)

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer thereb ...

Nicholas A Schmitz: Apparatus and method for allocation of resoures in programmable logic devices. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, July 7, 1992: US05128871 (198 worldwide citation)

Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation mea ...

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