11
William M Johnson: System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache. Advanced Micro Devices, Foley & Lardner, August 4, 1992: US05136697 (272 worldwide citation)

A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address ...


12
David Greenlaw: Three-dimensional integrated semiconductor devices. Advanced Micro Devices, Williams Morgan & Amerson P C, September 13, 2005: US06943067 (266 worldwide citation)

The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invent ...


13
Sergey Lopatin, Fei Wang, Diana Schonauer, Steven C Avanzino: Interconnect structure formed in porous dielectric material with minimized degradation and electromigration. Advanced Micro Devices, Monica H Choi, March 4, 2003: US06528409 (246 worldwide citation)

For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material be ...


14
John W Sliwa Jr: Method for coplanar integration of semiconductor ic devices. Advanced Micro Devices, David W Collins, February 5, 1991: US04990462 (245 worldwide citation)

A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'). Each segment is provided with at least one edge (12) having an ...


15
David B Witt, William M Johnson: High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, July 22, 1997: US05651125 (224 worldwide citation)

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and lo ...


16
John W Sliwa Jr: Method of coplanar integration of semiconductor IC devices. Advanced Micro Devices, Benman & Collins, December 24, 1991: US05075253 (222 worldwide citation)

A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'). Each segment is provided with at least one edge (12) having an ...


17
William M Johnson: Multiple instruction decoder for minimizing register port requirements. Advanced Micro Devices, Foley & Lardner, July 7, 1992: US05129067 (220 worldwide citation)

A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand ide ...


18
Arvind Halliyal, Mark T Ramsbey, Kuo Tung Chang, Nicholas H Tripsas, Robert B Ogle: Use of high-k dielectric materials in modified ONO structure for semiconductor devices. Advanced Micro Devices, Renner Otto Boisselle & Sklar, January 6, 2004: US06674138 (220 worldwide citation)

A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the f ...


19
Sameer S Haddad, Chi Chang, Antonio Matalvo, Michael A Van Buskirk: Flash EEPROM array with negative gate voltage erase operation. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, December 31, 1991: US05077691 (217 worldwide citation)

A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed ...


20
Antonio J Montalvo, Michael A Van Buskirk: Flash EEPROM array with paged erase architecture. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, June 30, 1992: US05126808 (216 worldwide citation)

A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means fo ...



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