1
Youmans Albert P: Semiconductor structure, assembly and method. Signetics Corporation, September 25, 1973: US3761782 (143 worldwide citation)

The semiconductor structure consists of a semiconductor body having first and second major surfaces with the devices being formed in one surface and with the lead structure making contact to the devices being carried by the one surface. Contact is made to the devices solely from the second major sur ...


2
Cecil H Kaplinsky: Memory access controller. Signetics Corporation, Jack E Haken, James J Cannon Jr, May 26, 1987: US04669043 (143 worldwide citation)

The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a tra ...


3
Sheldon C P Lim, Douglas F Ridley, Saiyed A Raza, George W Conner: Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer. Signetics Corporation, R J Meetin, R Mayer, J Oisher, February 11, 1986: US04569121 (123 worldwide citation)

In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type ...


4
Marcos Karnezos: Ball grid array semiconductor package. Signetics KP, Martine Penilla & Kim, February 1, 2000: US06020637 (97 worldwide citation)

Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically i ...


5
Hans J Sigg, Ching W S Lai, Warren C Rosvold: Refractory metal contacts for IGFETS. Signetics Corporation, Jerry A Dinardo, Jack Oisher, February 20, 1979: US04141022 (83 worldwide citation)

A metal contact system for an IGFET having shallow source and drain includes a refractory metal silicide layer forming low resistance ohmic contact to a silicon surface, a layer on the silicide layer of another refractory metal to serve as a barrier against diffusion of the interconnect metal, and a ...


6
Deepraj S Puar: Depletion-mode FET for the regulation of the on-chip generated substrate bias voltage. Signetics Corporation, R J Meetin, J Oisher, T Briody, April 19, 1988: US04739191 (81 worldwide citation)

An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). ...


7
William T Stacy, Sheldon C P Lim, Kevin G Jew: Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation. Signetics Corporation, J A Dinardo, R Meetin, R Mayer, February 11, 1986: US04569120 (79 worldwide citation)

In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductiv ...


8
Drees Joseph M, Beyerlein Fritz W: Semiconductor lead structure and assembly and method for fabricating same. Signetics Corporation, Flehr Hohbach Test Albritton & Herbert, August 26, 1975: US3902148 (75 worldwide citation)

A lead structure formed from a sheet of electrically conducting material having a plurality of spaced integral lead arrays formed therein with each of the arrays comprising a plurality of first leads formed from the sheet material in one region thereof and being integral with the sheet with each of ...


9
Johan H Huijsing, Rudy J van de Plassche: Differential amplifier with rail-to-rail input capability and controlled transconductance. Signetics Corporation, R J Meetin, R Mayer, T A Briody, November 26, 1985: US04555673 (68 worldwide citation)

A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does ...


10
Deepraj S Puar: Semiconductor memory array. Signetics Corporation, Jerry A Dinardo, Robert T Mayer, Thomas A Briody, July 27, 1982: US04342102 (67 worldwide citation)

An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each ...



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