WO/2007/095080 is referenced by 79 patents.

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.

Title
Memory circuit system and method
Application Number
PCT/US2007/003460
Publication Number
2007/095080
Application Date
February 8, 2007
Publication Date
August 23, 2007
Inventor
Weber Frederick Daniel
Wang David T
Schakel Keith R
Smith Michael John Sebastian
Rajan Suresh Natarajan
Agent
KOTAB Dominic M
Assignee
Metaram
Weber Frederick Daniel
Wang David T
Schakel Keith R
Smith Michael John Sebastian
Rajan Suresh Natarajan
IPC
G06F 12/00
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