WO/2005/106891 is referenced by 6 patents.

Methods and circuits are presented for performing high speed write (programming) operations in a dual-bit flash memory array. The method (200) includes, for example, erasing (204) a first and second bit of each cell in the array to a first state, programming (206) the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array (402) having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit (404) configured to selectively block erase one of the array portions, wherein in a first phase of the block erase (204) both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit (404) is further configured to, in a second phase (206) of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

Methods and systems for high write performance in multi-bit flash memory devices
Application Number
Publication Number
Application Date
February 11, 2005
Publication Date
November 10, 2005
Kornitz Roni
Hamilton Darlene
Randolph Mark
Kornitz Roni
Hamilton Darlene
Randolph Mark
G11C 11/56
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