An apparatus and a method of fabricating a semiconductor device (10) including the steps of forming a gate dielectric layer (20) on a semiconductor substrate (12); forming a gate electrode (18) over the gate dielectric layer (20) wherein the gate electrode (20) defines a channel (22) interposed between source/drain regions (16c/16b) formed within an active region (14) of the semiconductor substrate (12); and forming contact etch resistant spacers (24) on sidewalls of the gate electrode (18) and sidewalls of the gate dielectric layer (20), the contact etch resistant spacers (24) are of a non-silicon oxide and a non-nitride material.

Title
Contact etch resistant spacers
Application Number
PCT/US2004/033412
Publication Number
2005/062372
Application Date
October 8, 2004
Publication Date
July 7, 2005
Inventor
Subramanian Ramkumar
Plat Marina V
Lyons Christopher F
Gabriel Calvin T
Agent
sDRAKE Paul S
Assignee
Subramanian Ramkumar
Plat Marina V
Lyons Christopher F
Gabriel Calvin T
Advanced Micro Devcies
IPC
H01L 21/60
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