RE036773 is referenced by 1 patents and cites 15 patents.

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

Title
Method for plating using nested plating buses and semiconductor device having the same
Application Number
136845
Publication Number
RE36773
Application Date
November 14, 1997
Publication Date
July 11, 2000
Inventor
Twila J Reeves
Round Rock
TX, US
John R Pastore
Leander
TX, US
Victor K Nomi
Austin
TX, US
Assignee
Motorola
IL, US
IPC
H05K 7/02
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