3921007 is referenced by 2 patents and cites 3 patents.

A logic circuit including a first multi-emitter input transistor for determining a logical AND function of input signals, a second multi-emitter transistor for amplifying the logical AND function and isolating the collector reactance and base circuitry of the input transistor from the remainder of the logic circuit, an output amplifier for transferring the amplified logical function to succeeding logic stages, and level shifting circuitry for preventing deterioration of the signal level of the output of the logic circuit. The level shifting circuitry includes elements for determining the input level necessary for initiating the level-shifting, a constant current sink and a current source.

Title
Standardizing logic gate
Application Number
05/458,877
Publication Number
3921007
Application Date
April 8, 1974
Publication Date
November 18, 1975
Inventor
Lacher William A
Agent
Chung Edmund M
Feeney Jr Edward J
Peterson Kevin R
Assignee
Burroughs Corporation
IPC
H03K 19/22
H03K 19/88
H03K 19/82
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