3909633 is referenced by 8 patents and cites 10 patents.

An input buffer circuit provides a series of output electronic pulses, substantially identical to each other and having relatively fast rise and fall times, even though the input pulses to the buffer may be unlike each other and have relatively slow rise and fall times. A first inverter receives and inverts the input pulses while a second inverter provides the uniform output pulses. A first latching circuit, comprised of a third and fourth inverter first opposes and then changes state to aid the inversion of a pulse by the first inverter resulting in a net speed-up of inversion. A second latching circuit first opposes and then changes state to aid the inversion, in the opposite direction, of a pulse by the first inverter resulting in a net speed-up of inversion in the opposite direction. The two latching circuits thereby provide an inverted pulse to the second inverter that has fast fall and rise time. This inverted pulse is nearly independent of the input pulse, except as to the triggering function of the first inverter, therefore, the pulses out of the second inverter are substantially identical.

Title
Wide bandwidth solid state input buffer
Application Number
05/529,781
Publication Number
3909633
Application Date
December 5, 1974
Publication Date
September 30, 1975
Inventor
Hall II David Wilson
Agent
Stevens Kenneth R
Rauner Vincent J
Assignee
Motorola
IPC
H03K 19/08
H03K 05/01
H03K 05/01
H03K 05/12
H03K 19/17
H03K 19/01
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