3865651 is referenced by 25 patents and cites 8 patents.

An improved method of manufacturing series gate type matrix circuits by a self-alignment technique is provided. In this method, the drain and the source of a selected MOS field-effect transistor are short-circuited by a diffused region of a semiconductivity type opposite to that of a silicon substrate and formed prior to the formation of a gate portion. This method eliminates the use of interconnecting conductors for short-circuiting the drains and the sources with the result that the surface area of the substrate which might have been occupied by such interconnecting conductors may be dispensed with to facilitate integration and moreover any desired matrix circuit may be formed by controlling conduction of such diffused regions.

Title
Method of manufacturing series gate type matrix circuits
Application Number
05/340,255
Publication Number
3865651
Application Date
March 12, 1973
Publication Date
February 11, 1975
Inventor
Arita Shigeru
Agent
Stevens Davis Miller & Mosher
Assignee
Matsushita Electronics Corporation
IPC
B01j 17/00
H01l 27/10
H01l 07/44
H01L 27/07
H01L 23/535
H01L 21/82
H01L 27/112
H01L 23/52
H01L 21/70
H01L 29/00
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