3845474 is referenced by 75 patents and cites 2 patents.

In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store embedded within for its individual use. A cache store in one processor might contain data from the communication tables which is obsoleted by operations of a second processor. The cache store clearing apparatus invalidates its data information any time its processor accesses the communication tables. The cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache store. The data in the cache store need not be cleared. Using the four level set associative tag directory permits the data information in the cache store to be invalidated by a 16 pulse burst of signals for 1K words of cache store directed to the tag directory indicators.

Cache store clearing operation for multiprocessor mode
Application Number
Publication Number
Application Date
November 5, 1973
Publication Date
October 29, 1974
Pine Donald L
Couleur John F
Lange Ronald Edwin
Hughes Edward W
Guernsey Lloyd B
Honeywell Information Systems
G06f 15/16
G06F 12/08
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