A data processing system with a central processing unit (CPU), main store (MS), and high speed storage (HSS) interposed between the CPU and store. The CPUhas a high degree of overlap and pipelining. That is, a plurality of instructions are buffered and predecoded through several stages prior to issuance to individual execution units where further instruction and operand buffering takes place. The execution units may be highly pipelined, wherein succeeding instructions can be issued to the execution unit prior to the completion of execution of a prior instruction. Additional hardware is added providing the ability to periodically establish a checkpoint which stores a minimum amount of CPU status information to permit processing to proceed with a plurality of instructions with the ability to cause the CPU to re-establish all of the data operated on and the status at the time the checkpoint was made.