3736566 is referenced by 123 patents and cites 5 patents.

A data processing system with a central processing unit (CPU), main store (MS), and high speed storage (HSS) interposed between the CPU and store. The CPUhas a high degree of overlap and pipelining. That is, a plurality of instructions are buffered and predecoded through several stages prior to issuance to individual execution units where further instruction and operand buffering takes place. The execution units may be highly pipelined, wherein succeeding instructions can be issued to the execution unit prior to the completion of execution of a prior instruction. Additional hardware is added providing the ability to periodically establish a checkpoint which stores a minimum amount of CPU status information to permit processing to proceed with a plurality of instructions with the ability to cause the CPU to re-establish all of the data operated on and the status at the time the checkpoint was made.

Central processing unit with hardware controlled checkpoint and retry facilities
Application Number
Publication Number
Application Date
August 18, 1971
Publication Date
May 29, 1973
Webster James J
Tomas William M
Sparacio Francis J
Johnson Lance H
Gustafson Richard N
Anderson David W
International Business Machines Corporation
G06f 11/04
G06F 09/38
G06F 11/14
G06F 09/40
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