3705332 is referenced by 32 patents and cites 3 patents.

An electrical circuit packaging structure and method of fabrication thereof. The packaging structure is comprised of one or more batch fabricated electrically conductive wafers stacked together under pressure to form a parallelpiped structure containing one or more active components (e.g., integrated circuit chips) as well as conductor means providing coaxial interconnections in X-, Y-, and Z-axis directions. A stack is normally comprised of conductive wafers of different types including component wafers, interconnection wafers, and connector wafers. Z-axis interconnections, i.e., through-connections in a wafer, are formed by slugs contained within the wafer profile extending between the top and bottom wafer surfaces. Each slug is surrounded by dielectric material which supports the slug and electrically isolates it from the remainder of the wafer material. X-Y axis interconnections are formed by conductors also contained within the wafer profile and surrounded by dielectric material providing support and electrical isolation. The Z-axis slugs and X-Y axis conductors are preferably formed in a wafer by selective chemical etching of the wafer from opposite surfaces thereof. The removed wafer material is replaced with dielectric material to physically support and electrically isolate the slug or conductor from the remaining wafer material.

Electrical circuit packaging structure and method of fabrication thereof
Application Number
Publication Number
Application Date
June 25, 1970
Publication Date
December 5, 1972
Parks Howard L
H05k 01/18
H05k 01/08
H01L 23/538
H01L 23/52
H01L 21/02
H01L 21/60
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