A circuit arrangement for interference suppression in which the signal is applied through a gating circuit blocked during interference to a storage capacitor which maintains the signal level constant during interference. To reduce the distortion, pulses are added to the signal thus obtained, which pulses occur after releasing the gating circuit and whose amplitude is proportional to the signal step occurring as a result of the release in the output signal of the gating circuit.The invention relates to a circuit arrangement for suppressing interferences in a receiver of electrical signals, which circuit arrangement includes a signal detector and an interference detector. The output signal from the signal detector is applied through a gating circuit to a storage capacitor and the output signal from the interference detector controls a first pulse shaper whose output pulses block the gating circuit during the occurrence of an interference pulseSuch a circuit arrangement is known from an Article in the magazine Alta Frequenza, vol. XXXVI, no. Aug. 8, 1967, pages 726- 731 and has been described in greater detail in co-pending U.S. Patent application Ser. No. 82,611, filed on Oct. 21, 1970. As soon as an interference pulse appears in the received signal the gating circuit is blocked so that the interference pulse is prevented from reaching the output signal. It is achieved with the aid of the storage capacitor that instead of the interference pulse the output signal is maintained at a level which corresponds to the signal level just before the occurrence of the interference pulse.Although an eminent suppression of interferences is obtained in this manner, it has been found that a noticeable distortion of the signal occurs in case of a large number of interferences. This is a result of the fact that a portion of the signal is cut off at every interference, namely a positive portion when the interference coincides with a positive going edge of the signal and a negative portion when the interference coincides with a negative going edge of the signal.It is an object of the present invention to obviate this drawback and to this end the circuit arrangement according to the invention is characterized by a second pulse shaper which is started by the first pulse shaper as soon as the pulse from the first pulse shaper is finished a modulation means for varies the amplitude of the output pulses from the second pulse shaper proportionally to the potential change which occurs in the output voltage of the gating circuit when this gating circuit is released. A means combines the output voltage of the gating circuit and the output pulses from these modulation means.The invention is based on the recognition of the fact that after a portion has been cut off from the signal as a result of an interference an equally large opposite portion is added to the signal again. The then residual error only includes components of comparatively high frequencies which are usually little noticeable, while the influence of suppressing the signal is completely eliminated in the comparatively low and well noticeable frequency components of the signal.