Gate protection is given to a complementary metal oxide semiconductor (CMOS) devices against excessive input voltage transients. An input diode which has a lower breakdown voltage than the gate oxide is attached to the input terminal to protect the gate oxide. The input protect diode is formed by diffusing an N+ region which overlaps both a P tube and an N substrate. The diffusion concentrations between the various regions determine the breakdown voltage of the protection diode. The overlapping relationship of the N+ diffusion over the P- tub and N substrate creates a structure which prevents parasitic NPN action.