3582713 is referenced by 34 patents and cites 3 patents.

A combined overload and overvoltage protective circuit for solid state devices which utilizes two transistors in a NOR logic gate configuration that is held normally off by a common emitter bias supplied through a feedback current developed from voltage supplied to a load. Either transistor is switched on to shunt supply current away from solid state devices of the circuit during an overload or input overvoltage condition.In case of overload, excessive load current causes the development of an increased drop across the base-emitter circuit of one transistor countering the hold off bias developed from the feedback current.An input overvoltage causes a Zener diode to conduct and to develop an increased drop across base-emitter of other transistor countering the same hold off bias developed from the feedback current.

Overcurrent and overvoltage protection circuit for a voltage regulator
Application Number
Publication Number
Application Date
March 16, 1970
Publication Date
June 1, 1971
Till James Peter
AMP Incorporated
G05f 01/58
H02h 03/20
G05F 01/10
G05F 01/571
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