3573573 is referenced by 16 patents and cites 5 patents.

This specification describes semiconductor storage cells for use in monolithic memories. These cells each have two planar transistors formed on a single surface of a monolithic chip. The planar transistors are coupled together to form a bistable circuit and are supplied power from a voltage distribution layer of the chip under the planar transistors so that the load elements for the storage cells are formed vertically through the monolithic chip between the voltage distribution layer and the planar transistors.

Memory cell with buried load impedances
Application Number
Publication Number
Application Date
December 23, 1968
Publication Date
April 6, 1971
Moore Richard L
International Business Machines Corporation
H01l 19/00
H01L 27/07
H01L 27/00
H01L 29/8605
H01L 29/66
H01L 29/02
H01L 29/08
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