3564226 is referenced by 16 patents and cites 4 patents.

A new electronic digital processor element has two groups of zero-delay registers, a single zero-delay adder, and zero-delay gates arranged to transfer information in the registers to the adder input terminals and to transfer information output from the adder to the registers. All information transfers between the registers are by way of the adder and are controlled by sets of simultaneous level-type signals selectively applied to the gates.

Title
Parallel binary processing system having minimal operational delay
Application Number
04/604,956
Publication Number
3564226
Application Date
December 27, 1966
Publication Date
February 16, 1971
Inventor
Seligman Lawrence
Assignee
Digital Equipment
IPC
G06f 07/52
G06f 07/50
G06F 15/78
G06F 15/76
G06F 07/48
G06F 07/57
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