09934354 is referenced by 1 patents and cites 110 patents.

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Title
Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design
Application Number
15/205593
Publication Number
9934354 (B1)
Application Date
July 8, 2016
Publication Date
April 3, 2018
Inventor
Ritabrata Bhattacharya
Malviya Nagar
IN
Nikhil Gupta
Vasant Kunj
IN
Madhur Sharma
Ghaziabad
IN
Abhishek Dabral
Noida
IN
Vikrant Khanna
Noida
IN
Arnold Ginetti
Antibes
FR
Steven R Durrill
Campbell
CA, US
Balvinder Singh
Faridabad
IN
Taranjit Singh Kukal
Nirankari Colony
IN
Agent
Vista IP Law Group
Assignee
Cadence Design Systems
CA, US
IPC
G06F 17/50
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