09881119 cites 109 patents.

Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.

Title
Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics
Application Number
14/754535
Publication Number
9881119 (B1)
Application Date
June 29, 2015
Publication Date
January 30, 2018
Inventor
Arnold Ginetti
Antibes
FR
Steven R Durrill
Campbell
CA, US
Taranjit Singh Kukal
Delhi
IN
Agent
Vista IP Law Group
Assignee
Cadence Design Systems
CA, US
IPC
G06F 17/50
G06F 9/455
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