09804942 cites 7 patents.

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Title
Safety node in interconnect data buses
Application Number
14/717894
Publication Number
9804942 (B2)
Application Date
May 20, 2015
Publication Date
October 31, 2017
Inventor
James Frank Galeotos
Canton
MA, US
Gordon Cheung
Sudbury
MA, US
Matthew Puzey
Norwood
MA, US
Richard F Grafton
Abington
MA, US
John A Hayden
Sharon
MA, US
Agent
Patent Capital Group
Assignee
ANALOG DEVICES
MA, US
IPC
G06F 13/40
G06F 13/42
G06F 13/364
G06F 11/07
G06F 11/30
G06F 11/00
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