09773695 is referenced by 19 patents and cites 1460 patents.

Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Title
Integrated bit-line airgap formation and gate stack post clean
Application Number
15/332910
Publication Number
9773695 (B2)
Application Date
October 24, 2016
Publication Date
September 26, 2017
Inventor
Nitin K Ingle
San Jose
CA, US
Shankar Venkataraman
Fremont
CA, US
Randhir Thakur
Fremont
CA, US
Vinod R Purayath
Los Gatos
CA, US
Agent
Kilpatrick Townsend & Stockton
Assignee
Applied Materials
CA, US
IPC
H01J 37/32
H01L 29/788
H01L 21/687
H01L 21/67
H01L 21/02
H01L 29/66
H01L 21/28
H01L 29/06
H01L 21/311
H01L 27/11568
H01L 21/764
View Original Source