09665372 is referenced by 9 patents and cites 98 patents.

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

Title
Parallel slice processor with dynamic instruction stream mapping
Application Number
14/274927
Publication Number
9665372 (B2)
Application Date
May 12, 2014
Publication Date
May 30, 2017
Inventor
Albert James Van Norstrand Jr
Round Rock
TX, US
Brian William Thompto
Austin
TX, US
Bruce Joseph Ronchetti
Austin
TX, US
Jose Eduardo Moreira
Irvington
NY, US
Jentje Leenstra
Bondorf
DE
Hung Qui Le
Austin
TX, US
Lee Evan Eisen
Round Rock
TX, US
Agent
Steven L Bennett
Andrew M Harris
Mitch Harris Atty at Law
Assignee
INTERNATIONAL BUSINESS MACHINES CORPORATION
NY, US
IPC
G06F 9/48
G06F 9/50
G06F 9/30
G06F 15/80
G06F 9/46
G06F 9/38
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