09318862 is referenced by 2 patents and cites 435 patents.

An electrical interconnect including a substrate with at least two adjacent layers configured to translate relative to each other between a nominal position and a translated position. A plurality of through holes are formed through the layers from a first surface of the substrate to a second surface of the substrate in both the nominal position and the translated position. At least one contact member is positioned in the through holes with distal portions accessible from the first surface and a proximal portions positioned near the second surface. The proximal portion of the contact members are secured to the substrate near the second surface with a conductive structure. The two adjacent layers of the substrate are translated from the nominal position to the translated position to elastically deform the contact members within the through holes and to displace the distal portions of the contact members toward the conductive structures, respectively.

Method of making an electronic interconnect
Application Number
Publication Number
9318862 (B2)
Application Date
April 16, 2014
Publication Date
April 19, 2016
Jim Rathburn
Maple Grove
HSIO Technologies
H01R 13/436
H01R 13/193
H01R 13/24
H01R 12/71
H01R 43/18
H05K 3/02
H05K 3/00
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