09128858 is referenced by 5 patents and cites 69 patents.

Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.

Title
Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values
Application Number
13/752757
Publication Number
9128858 (B1)
Application Date
January 29, 2013
Publication Date
September 8, 2015
Inventor
Ihab Jaser
San Jose
CA, US
Christopher I W Norrie
San Jose
CA, US
Alessia Marelli
Dalmine
IT
Peter Z Onufryk
Flanders
NJ, US
Rino Micheloni
Turate
IT
Agent
Mark Peloquin
Kenneth Glass
Glass & Associates
Assignee
PMC SIERRA US
CA, US
IPC
G06F 11/10
G11C 29/00
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