09070477 is referenced by 2 patents and cites 550 patents.

A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.

Title
Bit interleaved low voltage static random access memory (SRAM) and related methods
Application Number
14/104182
Publication Number
9070477 (B1)
Application Date
December 12, 2013
Publication Date
June 30, 2015
Inventor
Lawrence T Clark
Phoenix
AZ, US
Agent
Baker Botts L
Assignee
Mie Fujitsu Semiconductor
JP
IPC
G11C 11/412
G11C 11/419
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