09047193 is referenced by 102 patents and cites 7 patents.

A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.

Title
Processor-cache system and method
Application Number
13/520572
Publication Number
9047193 (B2)
Application Date
January 28, 2011
Publication Date
June 2, 2015
Inventor
Haoqi Ren
Shanghai
CN
Kenneth Chenghao Lin
Shanghai
CN
Agent
Anova Law Group PLLC
Assignee
SHANGHAI XIN HAO MICRO ELECTRONICS
CN
IPC
G06F 9/30
G06F 12/08
G06F 9/34
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