09009642 cites 29 patents.

An apparatus includes a memory device that includes instructions for analyzing RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The instructions can include receiving RTL code, and identifying a statement in the RTL code. The instructions can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The instructions can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The instructions can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group.

Title
Congestion estimation techniques at pre-synthesis stage
Application Number
14/60220
Publication Number
9009642 (B1)
Application Date
October 22, 2013
Publication Date
April 14, 2015
Inventor
Dilip K Jha
Bangalore
IN
Sourav Saha
Barrackpur
IN
Agent
DeLizio Gilliam PLLC
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 17/50
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