08989202 is referenced by 4 patents and cites 549 patents.

A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Title
Pipeline method and system for switching packets
Application Number
13/398725
Publication Number
8989202 (B2)
Application Date
February 16, 2012
Publication Date
March 24, 2015
Inventor
Aris Wong
San Jose
CA, US
Ian Edward Davis
Fremont
CA, US
Agent
Kilpatrick Townsend & Stockton
Assignee
Foundry Networks
CA, US
IPC
H04L 12/933
H04L 12/66
H04L 12/28
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