08977885 cites 10 patents.

A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.

Title
Programmable logic device data rate booster for digital signal processing
Application Number
13/412408
Publication Number
8977885 (B1)
Application Date
March 5, 2012
Publication Date
March 10, 2015
Inventor
Asher Hazanchuk
Sunnyvale
CA, US
Assignee
Lattice Semiconductor Corporation
OR, US
IPC
G06F 5/06
G06F 1/04
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