08627253 is referenced by 1 patents and cites 5 patents.

In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

Title
Method for substrate noise analysis
Application Number
12/766732
Publication Number
8627253 (B2)
Application Date
April 23, 2010
Publication Date
January 7, 2014
Inventor
Fu Lung Hsueh
Cranbury
NJ, US
Sally Liu
Hsin-Chu
TW
Chewn Pu Jou
Hsin-Chu
TW
Kal Wen Tan
Taipei
TW
Tzu Jin Yeh
Hsin-Chu
TW
Agent
Slater & Matsil L
Assignee
Taiwan Semiconductor Manufacturing Company
TW
IPC
G06F 17/50
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